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sayma_rtm: drive clk_src_ext_sel

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Sebastien Bourdeauducq 2019-12-09 19:47:50 +08:00
parent b6f7698a69
commit d159d0e901
1 changed files with 2 additions and 0 deletions
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2
artiq/gateware/targets/sayma_rtm.py
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@ -185,6 +185,8 @@ class Satellite(_SatelliteBase):
self.add_rtio(rtio_channels) self.add_rtio(rtio_channels)
self.comb += platform.request("clk_src_ext_sel").eq(0)
# HMC clock chip and DAC control # HMC clock chip and DAC control
self.comb += [ self.comb += [
platform.request("ad9154_rst_n", 0).eq(1), platform.request("ad9154_rst_n", 0).eq(1),