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ttl: Remove broken TTLClockGen.sync 

The code currently doesn't compile because of a typo in the timestamp
field name. However, tracking event timestamps in software is
problematic anyway (e.g. with DMA, see GitHub #1113), so just remove
`sync()` altogether.
This commit is contained in:
David Nadlinger 2018-07-23 12:28:45 +01:00 committed by Sébastien Bourdeauducq
parent 7f11411127
commit cbfbe24d7a
1 changed files with 0 additions and 10 deletions
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10
artiq/coredevice/ttl.py
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@ -378,8 +378,6 @@ class TTLClockGen:
self.core = dmgr.get(core_device) self.core = dmgr.get(core_device)
self.channel = channel self.channel = channel
# in RTIO cycles
self.previous_timestamp = numpy.int64(0)
self.acc_width = numpy.int64(24) self.acc_width = numpy.int64(24)
@portable @portable
@ -415,7 +413,6 @@ class TTLClockGen:
that are not powers of two cause jitter of one RTIO clock cycle at the that are not powers of two cause jitter of one RTIO clock cycle at the
output.""" output."""
rtio_output(now_mu(), self.channel, 0, frequency) rtio_output(now_mu(), self.channel, 0, frequency)
self.previous_timestamp = now_mu()
@kernel @kernel
def set(self, frequency): def set(self, frequency):
@ -426,10 +423,3 @@ class TTLClockGen:
def stop(self): def stop(self):
"""Stop the toggling of the clock and set the output level to 0.""" """Stop the toggling of the clock and set the output level to 0."""
self.set_mu(0) self.set_mu(0)
@kernel
def sync(self):
"""Busy-wait until all programmed frequency switches and stops have
been effected."""
while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
pass