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artiq_flash: fix gateware header not in little-endian for RISC-V

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Harry Ho 2021-10-21 15:00:48 +08:00 committed by Sébastien Bourdeauducq
parent 0aa8a739aa
commit c940f104f1
1 changed files with 2 additions and 2 deletions
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4
artiq/frontend/artiq_flash.py
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@ -418,8 +418,8 @@ def main():
magic = 0x5352544d # "SRTM", see sayma_rtm target magic = 0x5352544d # "SRTM", see sayma_rtm target
length = bin_file.tell() - 8 length = bin_file.tell() - 8
bin_file.seek(0) bin_file.seek(0)
bin_file.write(magic.to_bytes(4, byteorder="big")) bin_file.write(magic.to_bytes(4, byteorder="little"))
bin_file.write(length.to_bytes(4, byteorder="big")) bin_file.write(length.to_bytes(4, byteorder="little"))
atexit.register(lambda: os.unlink(bin_filename)) atexit.register(lambda: os.unlink(bin_filename))
return bin_filename return bin_filename