forked from M-Labs/artiq
test: add test for short RTIO input gate
Based on https://github.com/m-labs/artiq/pull/1136 See also https://github.com/m-labs/artiq/issues/1137
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@ -178,6 +178,61 @@ class LoopbackCount(EnvExperiment):
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self.set_dataset("count", self.loop_in.count())
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class IncorrectPulseTiming(Exception):
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pass
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class LoopbackGateTiming(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("loop_in")
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self.setattr_device("loop_out")
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@kernel
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def run(self):
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# Make sure there are no leftover events.
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self.core.reset()
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# Determine loop delay.
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with parallel:
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self.loop_in.gate_rising_mu(10000)
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with sequential:
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delay_mu(5000)
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out_mu = now_mu()
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self.loop_out.pulse_mu(1000)
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in_mu = self.loop_in.timestamp_mu()
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if in_mu < 0:
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raise PulseNotReceived("Cannot determine loop delay")
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loop_delay_mu = in_mu - out_mu
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# With the exact delay known, make sure tight gate timings work.
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# In the most common configuration, 24 mu == 24 ns == 3 coarse periods,
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# which should be plenty of slack.
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delay_mu(10000)
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gate_start_mu = now_mu()
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self.loop_in.gate_both_mu(24)
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gate_end_mu = now_mu()
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# gateware latency offset between gate and input
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lat_offset = 3*8
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out_mu = gate_start_mu - loop_delay_mu + lat_offset
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at_mu(out_mu)
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self.loop_out.pulse_mu(24)
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in_mu = self.loop_in.timestamp_mu()
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if in_mu < 0:
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raise PulseNotReceived()
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if not (gate_start_mu <= (in_mu - lat_offset) <= gate_end_mu):
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raise IncorrectPulseTiming("Input event should occur during gate")
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if not (-2 < (in_mu - out_mu - loop_delay_mu) < 2):
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raise IncorrectPulseTiming("Loop delay should not change")
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in_mu = self.loop_in.timestamp_mu()
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if in_mu > 0:
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raise IncorrectPulseTiming("Only one pulse should be received")
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class IncorrectLevel(Exception):
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pass
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@ -387,6 +442,9 @@ class CoredeviceTest(ExperimentCase):
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count = self.dataset_mgr.get("count")
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self.assertEqual(count, npulses)
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def test_loopback_gate_timing(self):
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self.execute(LoopbackGateTiming)
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def test_level(self):
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self.execute(Level)
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