From c78c5a2b4ff4d6996e9f67f889f696229dc7793e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 30 Nov 2014 01:00:52 +0800 Subject: [PATCH] rtio: fix guard cycle computation --- soc/artiqlib/rtio/core.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/soc/artiqlib/rtio/core.py b/soc/artiqlib/rtio/core.py index f13a8b2fd..ac44642de 100644 --- a/soc/artiqlib/rtio/core.py +++ b/soc/artiqlib/rtio/core.py @@ -61,10 +61,9 @@ class _RTIOCounter(Module): # # The buffer must be transferred to the FIFO soon enough to account for: # * transfer of counter to sys domain: Tio + 2*Tsys + Tsys -# * guard time detection latency: Tsys # * FIFO latency: Tsys + 2*Tio # Therefore we must choose: -# guard_io_cycles > (3*Tio + 5*Tsys)/Tio +# guard_io_cycles > (3*Tio + 4*Tsys)/Tio # # We are writing to the FIFO from the buffer when the guard time has been # reached without checking the FIFO's writable status. If the FIFO is full,