forked from M-Labs/artiq
sayma: add many-port pure DRTIO master
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84b3d9ecc6
commit
c750de2955
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@ -115,6 +115,9 @@ class RTMCommon:
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class Standalone(MiniSoC, AMPSoC, RTMCommon):
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"""
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Local DAC/SAWG channels only.
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"""
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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@ -216,7 +219,10 @@ class Standalone(MiniSoC, AMPSoC, RTMCommon):
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self.csr_devices.append("sysref_sampler")
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class Master(MiniSoC, AMPSoC, RTMCommon):
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class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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"""
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DRTIO master with local DAC/SAWG channels.
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"""
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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@ -358,7 +364,135 @@ class Master(MiniSoC, AMPSoC, RTMCommon):
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self.csr_devices.append("sysref_sampler")
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class Master(MiniSoC, AMPSoC):
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"""
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DRTIO master with 2 SFP ports plus 8 lanes on RTM.
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Use passive RTM adapter to connect to satellites.
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Due to GTH clock routing restrictions, it is not possible
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to use more RTM lanes without additional hardware.
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"""
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"drtio_aux": 0x14000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += [
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platform.request("sfp_tx_disable", i).eq(0)
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for i in range(2)
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]
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout", 0),
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data_pads=[platform.request("sfp", i) for i in range(2)] +
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[platform.request("rtm_gth", i) for i in range(8)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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drtio_csr_group = []
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drtio_memory_group = []
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drtio_cri = []
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for i in range(10):
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core_name = "drtio" + str(i)
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memory_name = "drtio" + str(i) + "_aux"
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drtio_csr_group.append(core_name)
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drtio_memory_group.append(memory_name)
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core = ClockDomainsRenamer({"rtio_rx": "rtio_rx"+str(i)})(
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DRTIOMaster(self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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memory_address = self.mem_map["drtio_aux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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core.aux_controller.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_memory_group("drtio_aux", drtio_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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for gth in self.drtio_transceiver.gths[1:]:
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth.rxoutclk)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + drtio_cri)
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self.register_kernel_cpu_csrdevice("cri_con")
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class Satellite(BaseSoC, RTMCommon):
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"""
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DRTIO satellite with local DAC/SAWG channels.
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Use SFP0 to connect to master (Kasli/Sayma).
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"""
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mem_map = {
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"serwb": 0x13000000,
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"drtio_aux": 0x14000000,
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@ -474,7 +608,7 @@ def main():
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parser.set_defaults(output_dir="artiq_sayma")
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parser.add_argument("-V", "--variant", default="standalone",
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help="variant: "
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"standalone/master/satellite "
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"standalone/masterdac/master/satellite "
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"(default: %(default)s)")
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parser.add_argument("--rtm-csr-csv",
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default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
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@ -488,6 +622,8 @@ def main():
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variant = args.variant.lower()
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if variant == "standalone":
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cls = Standalone
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elif variant == "masterdac":
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cls = MasterDAC
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elif variant == "master":
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cls = Master
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elif variant == "satellite":
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@ -496,6 +632,7 @@ def main():
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(with_sawg=not args.without_sawg, **soc_sdram_argdict(args))
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if variant != "master":
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remote_csr_regions = remote_csr.get_remote_csr_regions(
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soc.mem_map["serwb"] | soc.shadow_base,
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args.rtm_csr_csv)
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@ -14,7 +14,7 @@ requirements:
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run:
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- python >=3.5.3,<3.6
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- setuptools 33.1.1
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- migen 0.7 py35_51+git9929b23
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- migen 0.7 py35_66+gitdcfec40
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- misoc 0.11 py35_20+git2436a68d
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- jesd204b 0.7
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- microscope
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