From c656a5353247534f69f1aa397a4ddc48a023cf12 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 29 Oct 2016 21:28:01 +0800 Subject: [PATCH] kc705: clean up clock constraints --- artiq/gateware/targets/kc705.py | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 960623e8f..4e95bc604 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -146,20 +146,11 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") - self.rtio.cd_rsys.clk.attr.add("keep") self.rtio_crg.cd_rtio.clk.attr.add("keep") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") - - self.platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.) self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.) self.platform.add_false_path_constraints( self.rtio.cd_rsys.clk, - self.rtio_crg.cd_rtio.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + self.rtio_crg.cd_rtio.clk) self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio, self.get_native_sdram_if())