From c5d6a2ba1a06bb01e71e03d278f65a263d646525 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 10 Sep 2017 23:41:04 +0800 Subject: [PATCH] rtio/sed: more output network fixes --- artiq/gateware/rtio/sed/output_network.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/rtio/sed/output_network.py b/artiq/gateware/rtio/sed/output_network.py index 94cd0d094..d993a58aa 100644 --- a/artiq/gateware/rtio/sed/output_network.py +++ b/artiq/gateware/rtio/sed/output_network.py @@ -68,8 +68,10 @@ class OutputNetwork(Module): for _ in range(lane_count)] for node1, node2 in step: + k1 = Cat(step_input[node1].payload.channel, ~step_input[node1].valid) + k2 = Cat(step_input[node2].payload.channel, ~step_input[node2].valid) self.sync += [ - If(step_input[node1].payload.channel == step_input[node2].payload.channel, + If(k1 == k2, If(cmp_wrap(step_input[node1].seqn, step_input[node2].seqn), step_output[node1].eq(step_input[node2]), step_output[node2].eq(step_input[node1]) @@ -77,11 +79,9 @@ class OutputNetwork(Module): step_output[node1].eq(step_input[node1]), step_output[node2].eq(step_input[node2]) ), - If(step_input[node1].valid & step_input[node2].valid, - step_output[node1].replace_occured.eq(1), - step_output[node2].valid.eq(0) - ) - ).Elif(step_input[node1].payload.channel < step_input[node2].payload.channel, + step_output[node1].replace_occured.eq(1), + step_output[node2].valid.eq(0), + ).Elif(k1 < k2, step_output[node1].eq(step_input[node1]), step_output[node2].eq(step_input[node2]) ).Else(