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firmware: support moninj without DDS. Closes #650

This commit is contained in:
Sebastien Bourdeauducq 2017-01-04 11:25:52 +01:00
parent 455250b3f9
commit c08fc8aae9
2 changed files with 16 additions and 18 deletions
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28
artiq/firmware/runtime/moninj.rs
View File

@ -18,6 +18,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
match request {
Request::Monitor => {
#[cfg(has_dds)]
let mut dds_ftws = [0u32; (csr::CONFIG_RTIO_DDS_COUNT as usize *
csr::CONFIG_DDS_CHANNELS_PER_BUS as usize)];
let mut reply = Reply::default();
@ -43,22 +44,25 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
}
}
reply.dds_rtio_first_channel = csr::CONFIG_RTIO_FIRST_DDS_CHANNEL as u16;
reply.dds_channels_per_bus = csr::CONFIG_DDS_CHANNELS_PER_BUS as u16;
#[cfg(has_dds)]
{
reply.dds_rtio_first_channel = csr::CONFIG_RTIO_FIRST_DDS_CHANNEL as u16;
reply.dds_channels_per_bus = csr::CONFIG_DDS_CHANNELS_PER_BUS as u16;
for j in 0..csr::CONFIG_RTIO_DDS_COUNT {
unsafe {
csr::rtio_moninj::mon_chan_sel_write(
(csr::CONFIG_RTIO_FIRST_DDS_CHANNEL + j) as u8);
for i in 0..csr::CONFIG_DDS_CHANNELS_PER_BUS {
csr::rtio_moninj::mon_probe_sel_write(i as u8);
csr::rtio_moninj::mon_value_update_write(1);
dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
csr::rtio_moninj::mon_value_read() as u32;
for j in 0..csr::CONFIG_RTIO_DDS_COUNT {
unsafe {
csr::rtio_moninj::mon_chan_sel_write(
(csr::CONFIG_RTIO_FIRST_DDS_CHANNEL + j) as u8);
for i in 0..csr::CONFIG_DDS_CHANNELS_PER_BUS {
csr::rtio_moninj::mon_probe_sel_write(i as u8);
csr::rtio_moninj::mon_value_update_write(1);
dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
csr::rtio_moninj::mon_value_read() as u32;
}
}
}
reply.dds_ftws = &dds_ftws;
}
reply.dds_ftws = &dds_ftws;
trace!("{} <- {:?}", addr, reply);
buf.clear();

6
artiq/gateware/targets/phaser.py
View File

@ -230,12 +230,6 @@ class Phaser(MiniSoC, AMPSoC):
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
# TODO: get rid of those bogus DDS defines
# currently moninj in the runtime requires them
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 1
self.config["DDS_CHANNELS_PER_BUS"] = 1
self.submodules.rtio_crg = _PhaserCRG(
platform, self.ad9154.jesd.cd_jesd.clk)
self.csr_devices.append("rtio_crg")