forked from M-Labs/artiq
suservo: use new rtio_output() API
This commit is contained in:
parent
e8d58b35b4
commit
bec25cbaa0
|
@ -1,4 +1,4 @@
|
|||
from artiq.language.core import kernel, delay, now_mu, delay_mu, portable
|
||||
from artiq.language.core import kernel, delay, delay_mu, portable
|
||||
from artiq.language.units import us, ns
|
||||
from artiq.coredevice.rtio import rtio_output, rtio_input_data
|
||||
from artiq.coredevice import spi2 as spi
|
||||
|
@ -129,7 +129,7 @@ class SUServo:
|
|||
:param addr: Memory location address.
|
||||
:param value: Data to be written.
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, addr | WE, value)
|
||||
rtio_output((self.channel << 8) | addr | WE, value)
|
||||
delay_mu(self.ref_period_mu)
|
||||
|
||||
@kernel
|
||||
|
@ -140,7 +140,7 @@ class SUServo:
|
|||
|
||||
:param addr: Memory location address.
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, addr, 0)
|
||||
rtio_output((self.channel << 8) | addr, 0)
|
||||
return rtio_input_data(self.channel)
|
||||
|
||||
@kernel
|
||||
|
@ -262,7 +262,7 @@ class Channel:
|
|||
:param en_iir: IIR updates enable
|
||||
:param profile: Active profile (0-31)
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, 0,
|
||||
rtio_output(self.channel << 8,
|
||||
en_out | (en_iir << 1) | (profile << 2))
|
||||
|
||||
@kernel
|
||||
|
|
Loading…
Reference in New Issue