From bd9eec15c003ddd2ca4ef6a3139e426321690da7 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 29 May 2020 15:59:16 +0800 Subject: [PATCH] metlino: increase number of DRTIO links Seems OK with Vivado 2019.2. --- artiq/gateware/targets/metlino.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py index 65e3c2f0c..b9746848a 100755 --- a/artiq/gateware/targets/metlino.py +++ b/artiq/gateware/targets/metlino.py @@ -67,8 +67,7 @@ class Master(MiniSoC, AMPSoC): self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("cdr_clk_clean", 0), - # use only a few channels to work around Vivado bug - data_pads=[platform.request("mch_fabric_d", i) for i in range(3)], + data_pads=[platform.request("mch_fabric_d", i) for i in range(11)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver")