firmware/serwb: move prbs_test outside of wait_init, add wishbone_test

artiq/firmware/libboard_artiq/serwb.rs

@@ -28,6 +28,57 @@ unsafe fn debug_print(rtm: bool) {
     }
 }
 
+fn prbs_test() {
+    let prbs_test_cycles : u32 = 1<<22;
+    let prbs_test_us : u64 = ((prbs_test_cycles as u64)*40)/125; // 40 bits @125MHz linerate
+
+    unsafe {
+        info!("RTM to AMC Link test");
+        csr::serwb_phy_amc::control_prbs_cycles_write(prbs_test_cycles);
+        csr::serwb_phy_amc::control_prbs_start_write(1);
+        clock::spin_us(prbs_test_us*110/100); // PRBS test time + 10%
+        info!("{} errors", csr::serwb_phy_amc::control_prbs_errors_read());
+
+        info!("AMC to RTM Link test");
+        csr::serwb_phy_rtm::control_prbs_cycles_write(prbs_test_cycles);
+        csr::serwb_phy_rtm::control_prbs_start_write(1);
+        clock::spin_us(prbs_test_us*110/100); // PRBS test time + 10%
+        info!("{} errors", csr::serwb_phy_rtm::control_prbs_errors_read());
+    }
+}
+
+fn prng32(seed: &mut u32) -> u32 { *seed = 1664525 * *seed + 1013904223; *seed }
+
+fn wishbone_test() {
+    let test_length: u32 = 512;
+    let mut test_errors : u32 = 0;
+
+    let mut seed : u32;
+
+    info!("Wishbone test...");
+    unsafe {
+        // Alternate pseudo random write/read bursts of
+        // increasing size.
+        for length in 0..test_length {
+            // Pseudo random writes
+            seed = length;
+            for _ in 0..length {
+                csr::rtm_scratch::write_data_write(prng32(&mut seed));
+                csr::rtm_scratch::write_stb_write(1);
+            }
+            // Pseudo random reads
+            seed = length;
+            for _ in 0..length {
+                if csr::rtm_scratch::read_data_read() != prng32(&mut seed) {
+                    test_errors += 1;
+                }
+                csr::rtm_scratch::read_ack_write(1);
+            }
+        }
+    }
+    info!("{} errors", test_errors);
+}
+
 pub fn wait_init() {
     info!("waiting for AMC/RTM serwb bridge to be ready...");
     unsafe {
@@ -42,22 +93,11 @@ pub fn wait_init() {
     }
     info!("done.");
 
-    unsafe {
+    // PRBS test
-        let prbs_test_cycles : u32 = 1<<22;
+    prbs_test();
-        let prbs_test_us : u64 = ((prbs_test_cycles as u64)*40)/125; // 40 bits @125MHz linerate
 
-        info!("RTM to AMC Link test");
+    // Wishbone test
-        csr::serwb_phy_amc::control_prbs_cycles_write(prbs_test_cycles);
+    wishbone_test();
-        csr::serwb_phy_amc::control_prbs_start_write(1);
-        clock::spin_us(prbs_test_us*110/100); // PRBS test time + 10%
-        info!("{} errors", csr::serwb_phy_amc::control_prbs_errors_read());
-
-        info!("AMC to RTM Link test");
-        csr::serwb_phy_rtm::control_prbs_cycles_write(prbs_test_cycles);
-        csr::serwb_phy_rtm::control_prbs_start_write(1);
-        clock::spin_us(prbs_test_us*110/100); // PRBS test time + 10%
-        info!("{} errors", csr::serwb_phy_rtm::control_prbs_errors_read());
-    }
 
     // Try reading the magic number register on the other side of the bridge.
     let rtm_magic = unsafe {