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gateware/eem: Force IOB=TRUE on Urukul SYNC output 

Without this, the final register in the SYNC signal TTLClockGen
isn't (always) placed in the I/O tile, leading to more jitter
than necessary, and causing "double window" artefacts. See
sinara-hw/Urukul#16 for more details.

(Patch based on work by Weida Zhang, testing by various members
of the community in Oxford and elsewhere.)
This commit is contained in:
David Nadlinger 2019-10-29 21:17:09 +00:00 committed by Sébastien Bourdeauducq
parent b25a17fa37
commit bc3b55b1a8
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/eem.py
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@ -87,7 +87,7 @@ class Urukul(_EEM):
), ),
] ]
ttls = [(6, eem, "io_update"), ttls = [(6, eem, "io_update"),
(7, eem, "dds_reset_sync_in")] (7, eem, "dds_reset_sync_in", Misc("IOB=TRUE"))]
if eem_aux is not None: if eem_aux is not None:
ttls += [(0, eem_aux, "sync_clk"), ttls += [(0, eem_aux, "sync_clk"),
(1, eem_aux, "sync_in"), (1, eem_aux, "sync_in"),
@ -97,12 +97,12 @@ class Urukul(_EEM):
(5, eem_aux, "sw1"), (5, eem_aux, "sw1"),
(6, eem_aux, "sw2"), (6, eem_aux, "sw2"),
(7, eem_aux, "sw3")] (7, eem_aux, "sw3")]
for i, j, sig in ttls: for i, j, sig, *extra_args in ttls:
ios.append( ios.append(
("urukul{}_{}".format(eem, sig), 0, ("urukul{}_{}".format(eem, sig), 0,
Subsignal("p", Pins(_eem_pin(j, i, "p"))), Subsignal("p", Pins(_eem_pin(j, i, "p"))),
Subsignal("n", Pins(_eem_pin(j, i, "n"))), Subsignal("n", Pins(_eem_pin(j, i, "n"))),
IOStandard(iostandard) IOStandard(iostandard), *extra_args
)) ))
return ios return ios