occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma/serwb: remove scrambling (does not seems to work on sayma for now...)

This commit is contained in:
Florent Kermarrec 2018-04-07 15:57:57 +02:00
parent 6aa8e2c433
commit bb90fb7d59
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/targets/sayma_amc.py
View File

@ -174,7 +174,7 @@ class Standalone(MiniSoC, AMPSoC):
self.submodules.serwb_phy_amc = serwb_phy_amc self.submodules.serwb_phy_amc = serwb_phy_amc
self.csr_devices.append("serwb_phy_amc") self.csr_devices.append("serwb_phy_amc")
serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True) serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=False)
self.submodules += serwb_core self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus) self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)

2
artiq/gateware/targets/sayma_rtm.py
View File

@ -161,7 +161,7 @@ class SaymaRTM(Module):
self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk) self.comb += self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.refclk)
csr_devices.append("serwb_phy_rtm") csr_devices.append("serwb_phy_rtm")
serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=True) serwb_core = serwb.core.SERWBCore(serwb_phy_rtm, int(clk_freq), mode="master", with_scrambling=False)
self.submodules += serwb_core self.submodules += serwb_core
# process CSR devices and connect them to serwb # process CSR devices and connect them to serwb