forked from M-Labs/artiq
suservo: docstring fixes, revert parametrization of r_rtt
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@ -443,15 +443,16 @@ class SUServo(_EEM):
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@classmethod
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def add_std(cls, target, eems_sampler, eems_urukul0, eems_urukul1,
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t_rtt=8, clk=1, shift=11, profile=5):
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""" Adds an 8-channel Sampler-Urukul servo to target.
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t_rtt=4, clk=1, shift=11, profile=5):
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"""Add a 8-channel Sampler-Urukul Servo
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:param t_rtt: upper estimate for clock round-trip propagation time from
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sck at the FPGA to clkout at the FPGA, measured in RTIO coarse
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cycles (default: 8). This is the sum of the round-trip cabling
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delay and the 8ns max propagation delay on Sampler. With all
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other parameters at their default values, increasing t_rtt beyond 8
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increases the servo latency
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``sck`` at the FPGA to ``clkout`` at the FPGA, measured in RTIO
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coarse cycles (default: 4). This is the sum of the round-trip
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cabling delay and the 8 ns max propagation delay on Sampler (ADC
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and LVDS drivers). Increasing ``t_rtt`` increases servo latency.
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With all other parameters at their default values, ``t_rtt`` values
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above 4 also increase the servo period (reduce servo bandwidth).
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:param clk: DDS SPI clock cycle half-width in RTIO coarse cycles
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(default: 1)
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:param shift: fixed-point scaling factor for IIR coefficients
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@ -459,7 +460,6 @@ class SUServo(_EEM):
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:param profile: log2 of the number of profiles for each DDS channel
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(default: 5)
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"""
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cls.add_extension(
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target, *(eems_sampler + eems_urukul0 + eems_urukul1))
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eem_sampler = "sampler{}".format(eems_sampler[0])
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@ -471,8 +471,9 @@ class SUServo(_EEM):
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target.platform, eem_urukul0, eem_urukul1)
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# timings in units of RTIO coarse period
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adc_p = servo.ADCParams(width=16, channels=8, lanes=4, t_cnvh=4,
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# account for SCK pipeline latency
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t_conv=57 - 4, t_rtt=t_rtt)
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# account for SCK DDR to CONV latency
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# difference (4 cycles measured)
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t_conv=57 - 4, t_rtt=t_rtt + 4)
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iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
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accu=48, shift=shift, channel=3,
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profile=profile)
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