occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

libdyld: accept objects with no rela relocations.

This commit is contained in:
whitequark 2019-06-17 06:43:34 +00:00
parent 0353966ef7
commit b8b9fa51bd
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/firmware/libdyld/lib.rs
View File

@ -289,7 +289,7 @@ impl<'a> Library<'a> {
if sym_ent != mem::size_of::<Elf32_Sym>() {
return Err("incorrect symbol entry size")?
}
if rela_ent != mem::size_of::<Elf32_Rela>() {
if rela_ent != 0 && rela_ent != mem::size_of::<Elf32_Rela>() {
return Err("incorrect relocation entry size")?
}