From b6586cd7e4bd4e7825d99502c76c4b813fefcd24 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Fri, 2 Sep 2022 20:45:13 +0000
Subject: [PATCH] add window data delay

---
 artiq/coredevice/phaser.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py
index 386c1897a..aa8c36819 100644
--- a/artiq/coredevice/phaser.py
+++ b/artiq/coredevice/phaser.py
@@ -1335,6 +1335,7 @@ class Miqro:
         for i in range(len(data)):
             addr += 1
             self.write32(addr, (data[i][0] & 0xffff) | (data[i][1] << 16))
+            delay(10*us)
 
     @kernel
     def pulse(self, window, profiles):