occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

jdcg: STPL tests now perform after DAC initialization

This commit is contained in:
Harry Ho 2020-12-15 17:55:48 +08:00 committed by Sébastien Bourdeauducq
parent 433c3bb8f9
commit b5405dfad6
2 changed files with 17 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
artiq/firmware/satman/jdcg.rs
View File

@ -108,10 +108,6 @@ pub mod jdac {
basic_request(dacno, jdac_common::PRBS, 0)?; basic_request(dacno, jdac_common::PRBS, 0)?;
jesd::prbs(dacno, false); jesd::prbs(dacno, false);
jesd::stpl(dacno, true);
basic_request(dacno, jdac_common::STPL, 0)?;
jesd::stpl(dacno, false);
basic_request(dacno, jdac_common::INIT, 0)?; basic_request(dacno, jdac_common::INIT, 0)?;
clock::spin_us(5000); clock::spin_us(5000);
@ -120,7 +116,22 @@ pub mod jdac {
return Err("JESD core reported bad SYNC"); return Err("JESD core reported bad SYNC");
} }
info!(" ...done"); info!(" ...done initializing");
}
Ok(())
}
pub fn stpl() -> Result<(), &'static str> {
for dacno in 0..csr::JDCG.len() {
let dacno = dacno as u8;
info!("Running STPL test on DAC-{}...", dacno);
jesd::stpl(dacno, true);
basic_request(dacno, jdac_common::STPL, 0)?;
jesd::stpl(dacno, false);
info!(" ...done STPL test");
} }
Ok(()) Ok(())
} }

1
artiq/firmware/satman/main.rs
View File

@ -594,6 +594,7 @@ pub extern fn main() -> i32 {
jdcg::jesd::reset(false); jdcg::jesd::reset(false);
let _ = jdcg::jdac::init(); let _ = jdcg::jdac::init();
jdcg::jesd204sync::sysref_auto_align(); jdcg::jesd204sync::sysref_auto_align();
jdcg::jdac::stpl();
unsafe { unsafe {
csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); // unhide csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); // unhide
} }