From b3697f951a93bfc28145a40b628c4668190eef01 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 3 Feb 2017 12:00:36 +0800 Subject: [PATCH] drtio: forward clocks to SMA connectors for debugging --- artiq/gateware/targets/kc705_drtio_master.py | 5 +++++ artiq/gateware/targets/kc705_drtio_satellite.py | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index c14d0ce68..f1636fa16 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -78,6 +78,11 @@ class Master(MiniSoC, AMPSoC): self.drtio.aux_controller.bus) self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800) + self.comb += [ + platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")), + platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) + ] + rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period) diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py index 1bed87451..2c81db0b4 100755 --- a/artiq/gateware/targets/kc705_drtio_satellite.py +++ b/artiq/gateware/targets/kc705_drtio_satellite.py @@ -98,6 +98,11 @@ class Satellite(BaseSoC): self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 + self.comb += [ + platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")), + platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) + ] + rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period) platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)