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drtio: forward clocks to SMA connectors for debugging

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This commit is contained in:
Sebastien Bourdeauducq 2017-02-03 12:00:36 +08:00
parent 9c646801e3
commit b3697f951a
2 changed files with 10 additions and 0 deletions
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5
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -78,6 +78,11 @@ class Master(MiniSoC, AMPSoC):
self.drtio.aux_controller.bus)
self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
]
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)

5
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -98,6 +98,11 @@ class Satellite(BaseSoC):
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
]
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)