forked from M-Labs/artiq
kernel: flush cache before mod_init
This could be necessary as redirecting instructions from D$ directly to I$ as it seems. Related: https://github.com/SpinalHDL/VexRiscv/issues/137
This commit is contained in:
parent
d50e24acb1
commit
b091d8cb66
|
@ -498,6 +498,9 @@ pub unsafe fn main() {
|
||||||
|
|
||||||
ptr::write_bytes(__bss_start as *mut u8, 0, (_end - __bss_start) as usize);
|
ptr::write_bytes(__bss_start as *mut u8, 0, (_end - __bss_start) as usize);
|
||||||
|
|
||||||
|
board_misoc::cache::flush_cpu_dcache();
|
||||||
|
board_misoc::cache::flush_cpu_icache();
|
||||||
|
|
||||||
(mem::transmute::<u32, fn()>(__modinit__))();
|
(mem::transmute::<u32, fn()>(__modinit__))();
|
||||||
|
|
||||||
if let Some(typeinfo) = typeinfo {
|
if let Some(typeinfo) = typeinfo {
|
||||||
|
|
Loading…
Reference in New Issue