From b0661ec055e5811b0eb1db46cc196d7500b2fdfc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Mon, 28 Oct 2019 15:35:44 +0100
Subject: [PATCH] comm_analyzer: don't assume every message has data

close #1377
---
 artiq/coredevice/comm_analyzer.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/coredevice/comm_analyzer.py b/artiq/coredevice/comm_analyzer.py
index 13f75c500..9a418f561 100644
--- a/artiq/coredevice/comm_analyzer.py
+++ b/artiq/coredevice/comm_analyzer.py
@@ -360,8 +360,8 @@ class SPIMaster2Handler(WishboneHandler):
     def process_message(self, message):
         self.stb.set_value("1")
         self.stb.set_value("0")
-        data = message.data
         if isinstance(message, OutputMessage):
+            data = message.data
             address = message.address
             if address == 1:
                 logger.debug("SPI config @%d data=0x%08x",