From ad096f294c841bef9f95c85422a02a773acb02c4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Tue, 22 Sep 2020 15:35:19 +0000
Subject: [PATCH] phaser: add hitl test exercising the complete API

---
 artiq/test/coredevice/test_phaser.py | 34 ++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 artiq/test/coredevice/test_phaser.py

diff --git a/artiq/test/coredevice/test_phaser.py b/artiq/test/coredevice/test_phaser.py
new file mode 100644
index 000000000..18aac6a57
--- /dev/null
+++ b/artiq/test/coredevice/test_phaser.py
@@ -0,0 +1,34 @@
+import unittest
+from artiq.experiment import *
+from artiq.test.hardware_testbench import ExperimentCase
+from artiq.language.core import kernel, delay
+from artiq.language.units import us
+
+
+class PhaserExperiment(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("phaser0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        # The Phaser initialization performs a comprehensive test:
+        # * Fastlink bringup
+        # * Fastlink error counter
+        # * Board identification
+        # * Hardware identification
+        # * SPI write, readback, timing
+        # * Temperature readout
+        # * DAC identification, IOTEST, alarm sweep, PLL configuration, FIFO
+        #   alignmend
+        # * DUC+Oscillator configuration, data end-to-end verification and
+        #   readback
+        # * Attenuator write and readback
+        # * TRF bringup PLL locking
+        self.phaser0.init()
+
+
+class PhaserTest(ExperimentCase):
+    def test(self):
+        self.execute(PhaserExperiment)