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rtio: add input-only channel

This commit is contained in:
Robert Jördens 2016-10-01 02:36:03 +02:00
parent 279f0d568d
commit a91ed8394c
1 changed files with 32 additions and 0 deletions
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32
artiq/gateware/rtio/phy/ttl_serdes_7series.py
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@ -31,6 +31,32 @@ class _OSERDESE2_8X(Module):
o_O=pad, o_OB=pad_n) o_O=pad, o_OB=pad_n)
class _ISERDESE2_8X(Module):
def __init__(self, pad, pad_n=None):
self.o = Signal(8)
self.i = Signal(8)
self.oe = Signal()
# # #
pad_i = Signal()
i = self.i
self.specials += Instance("ISERDESE2", p_DATA_RATE="DDR",
p_DATA_WIDTH=8,
p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
o_Q1=i[7], o_Q2=i[6], o_Q3=i[5], o_Q4=i[4],
o_Q5=i[3], o_Q6=i[2], o_Q7=i[1], o_Q8=i[0],
i_D=pad_i,
i_CLK=ClockSignal("rtiox4"),
i_CLKB=~ClockSignal("rtiox4"),
i_CE1=1, i_RST=0,
i_CLKDIV=ClockSignal("rio_phy"))
if pad_n is None:
self.comb += pad_i.eq(pad)
else:
self.specials += Instance("IBUFDS", o_O=pad_i, i_I=pad, i_IB=pad_n)
class _IOSERDESE2_8X(Module): class _IOSERDESE2_8X(Module):
def __init__(self, pad, pad_n=None): def __init__(self, pad, pad_n=None):
self.o = Signal(8) self.o = Signal(8)
@ -80,3 +106,9 @@ class Inout_8X(ttl_serdes_generic.Inout):
serdes = _IOSERDESE2_8X(pad, pad_n) serdes = _IOSERDESE2_8X(pad, pad_n)
self.submodules += serdes self.submodules += serdes
ttl_serdes_generic.Inout.__init__(self, serdes) ttl_serdes_generic.Inout.__init__(self, serdes)
class Input_8X(ttl_serdes_generic.Inout):
def __init__(self, pad, pad_n=None):
serdes = _ISERDESE2_8X(pad, pad_n)
self.submodules += serdes
ttl_serdes_generic.Inout.__init__(self, serdes)