From a91836e5fe75476b6fb7041ba93cc2013eb3eb1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Tue, 6 Sep 2022 20:26:50 +0000 Subject: [PATCH] easier fix for dt --- artiq/gateware/rtio/phy/phaser.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/rtio/phy/phaser.py b/artiq/gateware/rtio/phy/phaser.py index 4ff1e7d42..d4658e828 100644 --- a/artiq/gateware/rtio/phy/phaser.py +++ b/artiq/gateware/rtio/phy/phaser.py @@ -99,7 +99,6 @@ class MiqroChannel(Module): self.ack = Signal() regs = [Signal(30, reset_less=True) for _ in range(3)] dt = Signal(7, reset_less=True) - dt_frame = Signal(6, reset_less=True) stb = Signal() pulse = Cat(stb, dt, regs) assert len(self.pulse) >= len(pulse) @@ -108,9 +107,11 @@ class MiqroChannel(Module): self.rtlink.o.busy.eq(stb & ~self.ack), ] self.sync.rtio += [ - dt_frame.eq(dt_frame + 1), + If(~stb, + dt.eq(dt + 2), + ), If(self.ack, - dt_frame.eq(0), + dt.eq(0), If(stb, [r.eq(0) for r in regs], ), @@ -119,7 +120,7 @@ class MiqroChannel(Module): If(self.rtlink.o.stb, Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data), If(self.rtlink.o.address == 0, - dt.eq(Cat(self.rtlink.o.fine_ts, dt_frame)), + dt[0].eq(self.rtlink.o.fine_ts), stb.eq(1), ), ),