forked from M-Labs/artiq
pipistrello: grow fifos a bit (may make ise happier)
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@ -151,7 +151,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
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self.rtio_crg.rtiox4_stb)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256,
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
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ofifo_depth=4))
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# the last TTL is used for ClockGen
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@ -166,7 +166,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = ttl_simple.Output(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128))
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rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
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phy = ttl_simple.Output(platform.request("ext_led", 0))
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self.submodules += phy
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@ -182,8 +182,8 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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for i in range(4, 8):
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phy = ttl_simple.Inout(pmod.d[i])
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=8,
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ofifo_depth=8))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
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ofifo_depth=128))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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@ -200,7 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.submodules += phy
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=8, ififo_depth=8))
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phy, ofifo_depth=128, ififo_depth=128))
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 8
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@ -210,7 +210,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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phy = dds.AD9858(dds_pins, 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=256,
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ofifo_depth=512,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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