From a7dd356d30b5fa106f4e52c29bd5d447c7affd31 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 7 Sep 2016 15:42:09 +0800 Subject: [PATCH] rtio/phy/ttl: support 'set sensitivity and sample' command (#218) --- artiq/gateware/rtio/phy/ttl_serdes_generic.py | 11 +++++++++-- artiq/gateware/rtio/phy/ttl_simple.py | 11 +++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/rtio/phy/ttl_serdes_generic.py b/artiq/gateware/rtio/phy/ttl_serdes_generic.py index 2ad163298..06bf186fc 100644 --- a/artiq/gateware/rtio/phy/ttl_serdes_generic.py +++ b/artiq/gateware/rtio/phy/ttl_serdes_generic.py @@ -90,14 +90,21 @@ class Inout(Module): # Input sensitivity = Signal(2) - self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2), - sensitivity.eq(self.rtlink.o.data)) + sample = Signal() + self.sync.rio += [ + sample.eq(0), + If(self.rtlink.o.stb & self.rtlink.o.address[1], + sensitivity.eq(self.rtlink.o.data), + If(self.rtlink.o.address[0], sample.eq(1)) + ) + ] i = serdes.i[-1] i_d = Signal() self.sync.rio_phy += [ i_d.eq(i), self.rtlink.i.stb.eq( + sample | (sensitivity[0] & ( i & ~i_d)) | (sensitivity[1] & (~i & i_d)) ), diff --git a/artiq/gateware/rtio/phy/ttl_simple.py b/artiq/gateware/rtio/phy/ttl_simple.py index a640cde5b..2192758df 100644 --- a/artiq/gateware/rtio/phy/ttl_simple.py +++ b/artiq/gateware/rtio/phy/ttl_simple.py @@ -59,8 +59,14 @@ class Inout(Module): ts.oe.eq(oe_k) ) ] - self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2), - sensitivity.eq(self.rtlink.o.data)) + sample = Signal() + self.sync.rio += [ + sample.eq(0), + If(self.rtlink.o.stb & self.rtlink.o.address[1], + sensitivity.eq(self.rtlink.o.data), + If(self.rtlink.o.address[0], sample.eq(1)) + ) + ] i = Signal() i_d = Signal() @@ -68,6 +74,7 @@ class Inout(Module): self.sync.rio_phy += i_d.eq(i) self.comb += [ self.rtlink.i.stb.eq( + sample | (sensitivity[0] & ( i & ~i_d)) | (sensitivity[1] & (~i & i_d)) ),