occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

targets/pipistrello: mon -> moninj

This commit is contained in:
Sebastien Bourdeauducq 2015-06-27 21:15:17 +02:00
parent c71fe29792
commit a7bbcdc1ad
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
soc/targets/artiq_pipistrello.py
View File

@ -60,7 +60,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
"rtio": None, # mapped on Wishbone instead "rtio": None, # mapped on Wishbone instead
"rtio_crg": 13, "rtio_crg": 13,
"kernel_cpu": 14, "kernel_cpu": 14,
"rtio_mon": 15 "rtio_moninj": 15
} }
csr_map.update(BaseSoC.csr_map) csr_map.update(BaseSoC.csr_map)
mem_map = { mem_map = {
@ -130,7 +130,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
clk_freq=125000000) clk_freq=125000000)
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width) self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width) self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
self.submodules.rtio_mon = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
# CPU connections # CPU connections
rtio_csrs = self.rtio.get_csrs() rtio_csrs = self.rtio.get_csrs()