From a533f2a0cd6c116c0a2311f489365b82dc22baf3 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 28 Apr 2023 14:49:55 +0800 Subject: [PATCH] rtio: SED, InputCollector use rio clock domain --- artiq/gateware/rtio/core.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index 1d9cfc006..52012379d 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -60,17 +60,17 @@ class Core(Module, AutoCSR): # Outputs/Inputs quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)] - outputs = SED(channels, tsc.glbl_fine_ts_width, + outputs = ClockDomainsRenamer("rio")(SED(channels, tsc.glbl_fine_ts_width, quash_channels=quash_channels, lane_count=lane_count, fifo_depth=fifo_depth, - interface=self.cri) + interface=self.cri)) self.submodules += outputs self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts) self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 12) - inputs = InputCollector(tsc, channels, + inputs = ClockDomainsRenamer("rio")(InputCollector(tsc, channels, quash_channels=quash_channels, - interface=self.cri) + interface=self.cri)) self.submodules += inputs # Asychronous output errors