From a2ff2cc1736663a77809a94867906368b84ea8fd Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 19 Jan 2019 11:47:50 +0800 Subject: [PATCH] sayma_amc: use more selective IOBUFDS false path --- artiq/gateware/targets/sayma_amc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 472331944..bba5d3711 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -406,9 +406,9 @@ def workaround_us_lvds_tristate(platform): # timing analysis. Disable the latter for IOBUFDS. # See: # https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364 - # FIXME: this is a bit zealous. Xilinx SR in progress to find a more selective command. platform.add_platform_command( - "set_false_path -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]") + "set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]" + " -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]") class Master(MiniSoC, AMPSoC):