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ad9154: re-adjust LMFCDel & LMFCVar for 1 GS/s (K=32) 

* @HarryMakes performed 25 consecutive power-cycles of Sayma, in 2-min intervals:
  * Results: MinDelay = 8, FALL_COUNT_Delay = 10
This commit is contained in:
Harry Ho 2021-12-06 17:52:50 +08:00
parent 2f49a1a412
commit a14666bc15
1 changed files with 2 additions and 2 deletions
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4
artiq/firmware/libboard_artiq/ad9154.rs
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@ -327,8 +327,8 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
// LMFCDel & LMFCVar were deduced from values of DYN_LINK_LATENCY_0 // LMFCDel & LMFCVar were deduced from values of DYN_LINK_LATENCY_0
// gathered from repeated power-cycles; see datasheet (Rev. C) p.44 // gathered from repeated power-cycles; see datasheet (Rev. C) p.44
// "Link Delay Setup Example, Without Known Delay" // "Link Delay Setup Example, Without Known Delay"
write(ad9154_reg::LMFC_DELAY_0, 10); write(ad9154_reg::LMFC_DELAY_0, 14);
write(ad9154_reg::LMFC_DELAY_1, 10); write(ad9154_reg::LMFC_DELAY_1, 14);
write(ad9154_reg::LMFC_VAR_0, 4); // receive buffer delay write(ad9154_reg::LMFC_VAR_0, 4); // receive buffer delay
write(ad9154_reg::LMFC_VAR_1, 4); write(ad9154_reg::LMFC_VAR_1, 4);
write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock