forked from M-Labs/artiq
savel_fpga: get rid of unneeded config
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parent
4912f53ab4
commit
a143e238a8
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@ -28,7 +28,7 @@ pub mod rpc_queue;
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#[cfg(has_si5324)]
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#[cfg(has_si5324)]
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pub mod si5324;
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pub mod si5324;
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#[cfg(has_slave_fpga)]
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#[cfg(has_slave_fpga_cfg)]
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pub mod slave_fpga;
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pub mod slave_fpga;
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#[cfg(has_serwb_phy_amc)]
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#[cfg(has_serwb_phy_amc)]
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pub mod serwb;
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pub mod serwb;
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@ -82,7 +82,7 @@ fn startup() {
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_ => info!("UART log level set to INFO by default")
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_ => info!("UART log level set to INFO by default")
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}
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}
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#[cfg(has_slave_fpga)]
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#[cfg(has_slave_fpga_cfg)]
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board_artiq::slave_fpga::load().expect("cannot load RTM FPGA gateware");
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board_artiq::slave_fpga::load().expect("cannot load RTM FPGA gateware");
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#[cfg(has_serwb_phy_amc)]
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#[cfg(has_serwb_phy_amc)]
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board_artiq::serwb::wait_init();
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board_artiq::serwb::wait_init();
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@ -194,8 +194,7 @@ class Standalone(MiniSoC, AMPSoC):
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slave_fpga_cfg.init_b,
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slave_fpga_cfg.init_b,
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slave_fpga_cfg.program_b,
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slave_fpga_cfg.program_b,
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])
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])
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self.csr_devices.append("slave_fpga_cfg")
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# self.csr_devices.append("slave_fpga_cfg")
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# self.config["HAS_SLAVE_FPGA"] = None
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self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
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self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
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# AMC/RTM serwb
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# AMC/RTM serwb
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