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gateware.spi: simpler clk bias

This commit is contained in:
Robert Jördens 2016-02-29 00:36:18 +01:00
parent d5893d15fb
commit 9a881aa430
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/spi.py
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@ -20,7 +20,7 @@ class SPIClockGen(Module):
cnt.eq(cnt - 1),
If(self.edge,
cnt.eq(self.load[1:] +
(self.load[0] & self.bias)),
(self.load[0] & (self.clk ^ self.bias))),
self.clk.eq(~self.clk),
)
]
@ -143,7 +143,7 @@ class SPIMachine(Module):
).Else(
self.cg.load.eq(self.div_read),
),
self.cg.bias.eq(fsm.before_entering("SETUP")),
self.cg.bias.eq(self.clk_phase),
fsm.ce.eq(self.cg.edge),
self.cs.eq(~fsm.ongoing("IDLE")),
self.reg.ce.eq(self.cg.edge),