From 9644a3a362e2fdf2d2a9d6d605a99dfa4d8d68d7 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 12 Oct 2016 15:00:53 +0200 Subject: [PATCH] ad9154: mix mode addr, digital gain must be on --- artiq/coredevice/ad9154_reg.py | 2 +- artiq/examples/phaser/repository/dac_setup.py | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/coredevice/ad9154_reg.py b/artiq/coredevice/ad9154_reg.py index 1f51d7315..6993745c1 100644 --- a/artiq/coredevice/ad9154_reg.py +++ b/artiq/coredevice/ad9154_reg.py @@ -748,7 +748,7 @@ def AD9154_GROUPCOMP_BYPI_GET(x: TInt32) -> TInt32: return (x >> 1) & 0x1 -AD9154_MIX_MODE = 0x047 +AD9154_MIX_MODE = 0x04a AD9154_NCOALIGN_MODE = 0x050 # default: 0x00, access: R/W diff --git a/artiq/examples/phaser/repository/dac_setup.py b/artiq/examples/phaser/repository/dac_setup.py index f9f9b5721..fdb02501b 100644 --- a/artiq/examples/phaser/repository/dac_setup.py +++ b/artiq/examples/phaser/repository/dac_setup.py @@ -106,7 +106,7 @@ class DACSetup(EnvExperiment): self.ad9154.dac_write(AD9154_DATAPATH_CTRL, AD9154_I_TO_Q_SET(0) | AD9154_SEL_SIDEBAND_SET(0) | AD9154_MODULATION_TYPE_SET(0) | AD9154_PHASE_ADJ_ENABLE_SET(0) | - AD9154_DIG_GAIN_ENABLE_SET(0) | AD9154_INVSINC_ENABLE_SET(0)) + AD9154_DIG_GAIN_ENABLE_SET(1) | AD9154_INVSINC_ENABLE_SET(0)) self.ad9154.dac_write(AD9154_IDAC_DIG_GAIN0, 0x00) self.ad9154.dac_write(AD9154_IDAC_DIG_GAIN1, 0x8) self.ad9154.dac_write(AD9154_QDAC_DIG_GAIN0, 0x00) @@ -181,8 +181,8 @@ class DACSetup(EnvExperiment): self.ad9154.dac_write(AD9154_CTRLREG1, jesd_settings.transport.f) self.ad9154.dac_write(AD9154_CTRLREG2, AD9154_ILAS_MODE_SET(0) | AD9154_THRESHOLD_MASK_EN_SET(0)) - self.ad9154.dac_write(AD9154_KVAL, 1) # *4*K multiframes during ILAS - self.ad9154.dac_write(AD9154_LANEENABLE, 0x0f) + self.ad9154.dac_write(AD9154_KVAL, 1) # *4*K multiframes during ILAS + self.ad9154.dac_write(AD9154_LANEENABLE, 0x0f) # CGS _after_ this self.ad9154.dac_write(AD9154_TERM_BLK1_CTRLREG0, 1) self.ad9154.dac_write(AD9154_TERM_BLK2_CTRLREG0, 1)