From 91e375ce6acd6b626b1040abefd1af7c1cdb9d63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Tue, 22 Jan 2019 09:36:21 +0000 Subject: [PATCH] ad9910: don't reset the input divide-by-two MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit suspected of causing weird PLL lock timout errors https://freenode.irclog.whitequark.org/m-labs/2019-01-22#1548148750-1548143221; Signed-off-by: Robert Jördens --- artiq/coredevice/ad9910.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index 1db942648..5ef117c38 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -347,7 +347,7 @@ class AD9910: # sync timing validation disable (enabled later) self.write32(_AD9910_REG_CFR2, 0x01010020) self.cpld.io_update.pulse(1*us) - cfr3 = (0x08078000 | (self.pll_vco << 24) | + cfr3 = (0x0807c000 | (self.pll_vco << 24) | (self.pll_cp << 19) | (self.pll_en << 8) | (self.pll_n << 1)) self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset