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dma: gate ddma features behind cfg(has_drtio)

This commit is contained in:
mwojcik 2023-03-27 17:06:20 +08:00 committed by Sébastien Bourdeauducq
parent e9a153b985
commit 9150230ea7
2 changed files with 31 additions and 23 deletions
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41
artiq/firmware/ksupport/lib.rs
View File

@ -405,6 +405,7 @@ extern fn dma_playback(timestamp: i64, ptr: i32) {
csr::cri_con::selected_write(1); csr::cri_con::selected_write(1);
csr::rtio_dma::enable_write(1); csr::rtio_dma::enable_write(1);
#[cfg(has_drtio)]
send(&DmaStartRemoteRequest { id: ptr as i32, timestamp: timestamp }); send(&DmaStartRemoteRequest { id: ptr as i32, timestamp: timestamp });
while csr::rtio_dma::enable_read() != 0 {} while csr::rtio_dma::enable_read() != 0 {}
csr::cri_con::selected_write(0); csr::cri_con::selected_write(0);
@ -427,23 +428,29 @@ extern fn dma_playback(timestamp: i64, ptr: i32) {
} }
} }
send(&DmaAwaitRemoteRequest { id: ptr as i32 }); #[cfg(has_drtio)]
recv!(&DmaAwaitRemoteReply { timeout, error, channel, timestamp } => { {
if timeout { send(&DmaAwaitRemoteRequest { id: ptr as i32 });
raise!("DMAError", recv!(&DmaAwaitRemoteReply { timeout, error, channel, timestamp } => {
"Error running DMA on satellite device, timed out waiting for results"); if timeout {
} println!("timeout\n");
if error & 1 != 0 { raise!("DMAError",
raise!("RTIOUnderflow", "Error running DMA on satellite device, timed out waiting for results");
"RTIO underflow at channel {rtio_channel_info:0}, {1} mu", }
channel as i64, timestamp as i64, 0); if error & 1 != 0 {
} println!("rtio underflow from ddma\n");
if error & 2 != 0 { raise!("RTIOUnderflow",
raise!("RTIODestinationUnreachable", "RTIO underflow at channel {rtio_channel_info:0}, {1} mu",
"RTIO destination unreachable, output, at channel {rtio_channel_info:0}, {1} mu", channel as i64, timestamp as i64, 0);
channel as i64, timestamp as i64, 0); }
} if error & 2 != 0 {
}); println!("rtio destun from ddma\n");
raise!("RTIODestinationUnreachable",
"RTIO destination unreachable, output, at channel {rtio_channel_info:0}, {1} mu",
channel as i64, timestamp as i64, 0);
}
});
}
} }
#[cfg(not(has_rtio_dma))] #[cfg(not(has_rtio_dma))]

13
artiq/firmware/runtime/rtio_dma.rs
View File

@ -218,12 +218,13 @@ impl Manager {
self.recording_trace.extend_from_slice(data) self.recording_trace.extend_from_slice(data)
} }
pub fn record_stop(&mut self, duration: u64, enable_ddma: bool, pub fn record_stop(&mut self, duration: u64, _enable_ddma: bool,
_io: &Io, _ddma_mutex: &Mutex) -> u32 { _io: &Io, _ddma_mutex: &Mutex) -> u32 {
let mut local_trace = Vec::new(); let mut local_trace = Vec::new();
let mut remote_traces: BTreeMap<u8, Vec<u8>> = BTreeMap::new(); let mut _remote_traces: BTreeMap<u8, Vec<u8>> = BTreeMap::new();
if enable_ddma { #[cfg(has_drtio)]
if _enable_ddma {
let mut trace = Vec::new(); let mut trace = Vec::new();
mem::swap(&mut self.recording_trace, &mut trace); mem::swap(&mut self.recording_trace, &mut trace);
trace.push(0); trace.push(0);
@ -239,10 +240,10 @@ impl Manager {
local_trace.extend(&trace[ptr..ptr+len]); local_trace.extend(&trace[ptr..ptr+len]);
} }
else { else {
if let Some(remote_trace) = remote_traces.get_mut(&destination) { if let Some(remote_trace) = _remote_traces.get_mut(&destination) {
remote_trace.extend(&trace[ptr..ptr+len]); remote_trace.extend(&trace[ptr..ptr+len]);
} else { } else {
remote_traces.insert(destination, trace[ptr..ptr+len].to_vec()); _remote_traces.insert(destination, trace[ptr..ptr+len].to_vec());
} }
} }
// and jump to the next event // and jump to the next event
@ -278,7 +279,7 @@ impl Manager {
self.name_map.insert(name, id); self.name_map.insert(name, id);
#[cfg(has_drtio)] #[cfg(has_drtio)]
remote_dma::add_traces(_io, _ddma_mutex, id, remote_traces); remote_dma::add_traces(_io, _ddma_mutex, id, _remote_traces);
id id
} }