occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sawg: advance dds 1/2 by one sample group 

closes #772
This commit is contained in:
Robert Jördens 2017-07-04 16:51:58 +02:00
parent 91ca9fbcad
commit 8e0a1cbdc8
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/dsp/sawg.py
View File

@ -163,7 +163,7 @@ class Channel(Module, SatAddMixin):
self.u.latency += 1 # self.o self.u.latency += 1 # self.o
b.p.latency += 1 # self.o b.p.latency += 1 # self.o
b.f.latency += 1 # self.o b.f.latency += 1 # self.o
a_latency_delta = hbf[0].latency + b.latency + 2 # hbf.i, self.o a_latency_delta = hbf[0].latency + b.latency + 3 # hbf.i, self.o
for a in a1, a2: for a in a1, a2:
a.a.latency += a_latency_delta a.a.latency += a_latency_delta
a.p.latency += a_latency_delta a.p.latency += a_latency_delta