forked from M-Labs/artiq
targets/kc705: redefine user SMAs as 3.3V IO. Closes #502
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@ -33,7 +33,7 @@ class _RTIOCRG(Module, AutoCSR):
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# 10 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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ext_clkout = platform.request("user_sma_gpio_p")
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ext_clkout = platform.request("user_sma_gpio_p_33")
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self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
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@ -79,6 +79,16 @@ class _RTIOCRG(Module, AutoCSR):
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]
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# The default user SMA voltage on KC705 is 2.5V, and the Migen platform
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# follows this default. But since the SMAs are on the same bank as the DDS,
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# which is set to 3.3V by reprogramming the KC705 power ICs, we need to
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# redefine them here.
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_sma33_io = [
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("user_sma_gpio_p_33", 0, Pins("Y23"), IOStandard("LVCMOS33")),
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("user_sma_gpio_n_33", 0, Pins("Y24"), IOStandard("LVCMOS33")),
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]
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_ams101_dac = [
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("ams101_dac", 0,
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Subsignal("ldac", Pins("XADC:GPIO0")),
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@ -131,6 +141,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.platform.request("user_led", 0),
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self.platform.request("user_led", 1)))
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self.platform.add_extension(_sma33_io)
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self.platform.add_extension(_ams101_dac)
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i2c = self.platform.request("i2c")
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@ -192,7 +203,7 @@ class NIST_QC1(_NIST_Ions):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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@ -248,7 +259,7 @@ class NIST_CLOCK(_NIST_Ions):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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@ -326,7 +337,7 @@ class NIST_QC2(_NIST_Ions):
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clock_generators.append(rtio.Channel.from_phy(phy))
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# user SMA on KC705 board
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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