forked from M-Labs/artiq
analyzer: use EOP, flush pipeline on stop
This commit is contained in:
parent
fc60f3504c
commit
8a6873cab2
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@ -19,6 +19,9 @@ InputMessage = namedtuple(
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ExceptionMessage = namedtuple(
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ExceptionMessage = namedtuple(
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"ExceptionMessage", "channel rtio_counter exception_type")
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"ExceptionMessage", "channel rtio_counter exception_type")
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StoppedMessage = namedtuple(
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"StoppedMessage", "rtio_counter")
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def decode_message(data):
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def decode_message(data):
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message_type_channel = struct.unpack(">I", data[28:32])[0]
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message_type_channel = struct.unpack(">I", data[28:32])[0]
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@ -37,6 +40,11 @@ def decode_message(data):
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exception_type, rtio_counter = struct.unpack(">BQ", data[11:20])
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exception_type, rtio_counter = struct.unpack(">BQ", data[11:20])
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return ExceptionMessage(channel, rtio_counter,
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return ExceptionMessage(channel, rtio_counter,
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ExceptionType(exception_type))
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ExceptionType(exception_type))
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elif message_type == MessageType.stopped:
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rtio_counter = struct.unpack(">Q", data[12:20])[0]
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return StoppedMessage(rtio_counter)
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else:
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raise ValueError
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DecodedDump = namedtuple(
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DecodedDump = namedtuple(
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@ -27,13 +27,23 @@ exception_layout = [
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("padding1", 88)
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("padding1", 88)
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]
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]
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assert layout_len(input_output_layout) == 256
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stopped_layout = [
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assert layout_len(exception_layout) == 256
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("message_type", 2),
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("padding0", 94),
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("rtio_counter", 64),
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("padding1", 96)
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]
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message_len = 256
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assert layout_len(input_output_layout) == message_len
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assert layout_len(exception_layout) == message_len
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assert layout_len(stopped_layout) == message_len
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class MessageEncoder(Module, AutoCSR):
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class MessageEncoder(Module, AutoCSR):
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def __init__(self, rtio_core):
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def __init__(self, rtio_core, enable):
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self.source = stream.Endpoint([("data", 256)])
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self.source = stream.Endpoint([("data", message_len)])
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self.overflow = CSRStatus()
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self.overflow = CSRStatus()
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self.overflow_reset = CSR()
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self.overflow_reset = CSR()
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@ -106,19 +116,37 @@ class MessageEncoder(Module, AutoCSR):
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)
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)
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]
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]
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self.sync += [
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stopped = Record(stopped_layout)
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If(exception_stb,
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self.comb += [
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self.source.data.eq(exception.raw_bits())
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stopped.message_type.eq(MessageType.stopped.value),
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).Else(
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stopped.rtio_counter.eq(
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self.source.data.eq(input_output.raw_bits())
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rtio_core.counter.value_sys << rtio_core.fine_ts_width),
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),
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self.source.stb.eq(input_output_stb | exception_stb)
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]
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]
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enable_r = Signal()
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stopping = Signal()
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self.sync += [
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self.sync += [
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If(self.overflow_reset.re, self.overflow.status.eq(0)),
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enable_r.eq(enable),
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If(self.source.stb & ~self.source.ack,
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If(~enable & enable_r, stopping.eq(1)),
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self.overflow.status.eq(1)
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If(~stopping,
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If(exception_stb,
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self.source.data.eq(exception.raw_bits())
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).Else(
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self.source.data.eq(input_output.raw_bits())
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),
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self.source.stb.eq(enable &
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(input_output_stb | exception_stb)),
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If(self.overflow_reset.re, self.overflow.status.eq(0)),
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If(self.source.stb & ~self.source.ack,
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self.overflow.status.eq(1)
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)
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).Else(
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self.source.data.eq(stopped.raw_bits()),
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self.source.eop.eq(1),
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self.source.stb.eq(1),
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If(self.source.ack, stopping.eq(0))
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)
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)
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]
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]
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@ -127,77 +155,86 @@ class DMAWriter(Module, AutoCSR):
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def __init__(self, membus):
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def __init__(self, membus):
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aw = len(membus.adr)
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aw = len(membus.adr)
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dw = len(membus.dat_w)
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dw = len(membus.dat_w)
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messages_per_dw = dw//message_len
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data_alignment = log2_int(dw//8)
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data_alignment = log2_int(dw//8)
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# shutdown procedure: set enable to 0, wait until busy=0
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self.enable = CSRStorage()
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self.busy = CSRStatus()
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self.reset = CSR() # only apply when shut down
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self.reset = CSR() # only apply when shut down
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# All numbers in bytes
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# All numbers in bytes
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self.base_address = CSRStorage(aw + data_alignment,
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self.base_address = CSRStorage(aw + data_alignment,
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alignment_bits=data_alignment)
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alignment_bits=data_alignment)
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self.last_address = CSRStorage(aw + data_alignment,
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self.last_address = CSRStorage(aw + data_alignment,
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alignment_bits=data_alignment)
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alignment_bits=data_alignment)
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self.byte_count = CSRStatus(64) # only read when shut down
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self.byte_count = CSRStatus(32) # only read when shut down
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self.sink = stream.Endpoint([("data", dw)])
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sink_layout = [("data", dw)]
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if messages_per_dw > 1:
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sink_layout.append(("valid_token_count",
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bits_for(messages_per_dw)))
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self.sink = stream.Endpoint(sink_layout)
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# # #
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# # #
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event_counter = Signal(63)
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self.comb += [
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self.comb += self.byte_count.status.eq(
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membus.stb.eq(self.sink.stb),
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event_counter << data_alignment)
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self.sink.ack.eq(membus.ack),
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membus.we.eq(1),
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membus.dat_w.eq(self.sink.data)
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]
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if messages_per_dw > 1:
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for i in range(dw//8):
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self.comb += membus.sel[i].eq(
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self.sink.valid_token_count >= i//(256//8))
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else:
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self.comb += membus.sel.eq(2**(dw//8)-1)
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fsm = FSM()
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self.sync += [
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.enable.storage & self.sink.stb,
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NextState("WRITE")
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),
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If(~self.enable.storage,
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self.sink.ack.eq(1)
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),
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If(self.reset.re,
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If(self.reset.re,
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NextValue(membus.adr, self.base_address.storage),
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membus.adr.eq(self.base_address.storage)),
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NextValue(event_counter, 0)
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)
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)
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fsm.act("WRITE",
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self.busy.status.eq(1),
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membus.cyc.eq(1),
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membus.stb.eq(1),
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If(membus.ack,
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If(membus.ack,
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If(membus.adr == self.last_address.storage,
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If(membus.adr == self.last_address.storage,
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NextValue(membus.adr, self.base_address.storage)
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membus.adr.eq(self.base_address.storage)
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).Else(
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).Else(
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NextValue(membus.adr, membus.adr + 1)
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membus.adr.eq(membus.adr + 1)
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),
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),
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NextValue(event_counter, event_counter + 1),
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self.sink.ack.eq(1),
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NextState("IDLE")
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)
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)
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)
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]
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self.comb += [
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membus.we.eq(1),
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event_counter = Signal(32)
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membus.sel.eq(2**len(membus.sel)-1),
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self.comb += self.byte_count.status.eq(
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membus.dat_w.eq(self.sink.data)
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event_counter << data_alignment)
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self.sync += [
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If(self.reset.re, event_counter.eq(0)),
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If(membus.ack, event_counter.eq(event_counter + 1))
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]
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]
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class Analyzer(Module, AutoCSR):
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class Analyzer(Module, AutoCSR):
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def __init__(self, rtio_core, membus, fifo_depth=128):
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def __init__(self, rtio_core, membus, fifo_depth=128):
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dw = len(membus.dat_w)
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# shutdown procedure: set enable to 0, wait until busy=0
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self.enable = CSRStorage()
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self.busy = CSRStatus()
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self.submodules.message_encoder = MessageEncoder(rtio_core)
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self.submodules.message_encoder = MessageEncoder(
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self.submodules.converter = stream.Converter(256, dw, reverse=True)
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rtio_core, self.enable.storage)
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self.submodules.fifo = stream.SyncFIFO(
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self.submodules.fifo = stream.SyncFIFO(
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[("data", dw)], fifo_depth, True)
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[("data", message_len)], fifo_depth, True)
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dw = len(membus.dat_w)
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self.submodules.converter = stream.Converter(
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message_len, dw, reverse=True,
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report_valid_token_count=dw > message_len)
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self.submodules.dma = DMAWriter(membus)
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self.submodules.dma = DMAWriter(membus)
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self.comb += [
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enable_r = Signal()
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self.message_encoder.source.connect(self.converter.sink),
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self.sync += [
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self.converter.source.connect(self.fifo.sink),
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enable_r.eq(self.enable.storage),
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self.fifo.source.connect(self.dma.sink)
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If(self.enable.storage & ~enable_r,
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self.busy.status.eq(1)),
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If(self.dma.sink.stb & self.dma.sink.ack & self.dma.sink.eop,
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self.busy.status.eq(0))
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]
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self.comb += [
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self.message_encoder.source.connect(self.fifo.sink),
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self.fifo.source.connect(self.converter.sink),
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self.converter.source.connect(self.dma.sink)
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]
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]
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@ -5,6 +5,7 @@ class MessageType(Enum):
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output = 0b00
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output = 0b00
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input = 0b01
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input = 0b01
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exception = 0b10
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exception = 0b10
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stopped = 0b11
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class ExceptionType(Enum):
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class ExceptionType(Enum):
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@ -27,13 +27,13 @@ static void arm(void)
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rtio_analyzer_dma_base_address_write((unsigned int)analyzer_buffer);
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rtio_analyzer_dma_base_address_write((unsigned int)analyzer_buffer);
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rtio_analyzer_dma_last_address_write((unsigned int)analyzer_buffer + ANALYZER_BUFFER_SIZE - 1);
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rtio_analyzer_dma_last_address_write((unsigned int)analyzer_buffer + ANALYZER_BUFFER_SIZE - 1);
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rtio_analyzer_dma_reset_write(1);
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rtio_analyzer_dma_reset_write(1);
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rtio_analyzer_dma_enable_write(1);
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rtio_analyzer_enable_write(1);
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}
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}
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static void disarm(void)
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static void disarm(void)
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{
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{
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rtio_analyzer_dma_enable_write(0);
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rtio_analyzer_enable_write(0);
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while(rtio_analyzer_dma_busy_read());
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while(rtio_analyzer_busy_read());
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flush_cpu_dcache();
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flush_cpu_dcache();
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flush_l2_cache();
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flush_l2_cache();
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}
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}
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