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rtio/dma: raise underflow in test

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This commit is contained in:
Sebastien Bourdeauducq 2017-10-09 10:22:58 +08:00
parent a9c9d5779d
commit 893be82ad1
1 changed files with 3 additions and 0 deletions
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3
artiq/gateware/test/rtio/test_dma.py
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@ -5,6 +5,7 @@ import itertools
from migen import *
from misoc.interconnect import wishbone
from artiq.coredevice.exceptions import RTIOUnderflow
from artiq.gateware import rtio
from artiq.gateware.rtio import dma, cri
from artiq.gateware.rtio.phy import ttl_simple
@ -56,6 +57,8 @@ def do_dma(dut, address):
yield
while ((yield from dut.enable.read())):
yield
if (yield from dut.cri_master.underflow.read()):
raise RTIOUnderflow
test_writes1 = [