From 8759c8d360e5e8158fda0edcebf55be3ba264b12 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 21 Dec 2019 14:17:22 +0800
Subject: [PATCH] shiftreg: fix get method

---
 artiq/coredevice/shiftreg.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/artiq/coredevice/shiftreg.py b/artiq/coredevice/shiftreg.py
index cf7b9466c..79000eba3 100644
--- a/artiq/coredevice/shiftreg.py
+++ b/artiq/coredevice/shiftreg.py
@@ -43,7 +43,8 @@ class ShiftReg:
         data = 0
         for i in range(self.n):
             data <<= 1
-            if self.ser_in.sample_input():
+            self.ser_in.sample_input()
+            if self.ser_in.sample_get():
                 data |= 1
             delay(self.dt)
             self.clk.on()