From 86825a852c8a8577ec3b37b79a171576d758e69a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 21 Dec 2017 23:52:44 +0100 Subject: [PATCH] gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200 --- artiq/gateware/targets/sayma_rtm.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 256637c4e..df9206dc5 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -77,6 +77,10 @@ class SaymaRTM(Module): self.crg.cd_sys.clk.attr.add("keep") clk_freq = 125e6 platform.add_period_constraint(self.crg.cd_sys.clk, 8.0) + platform.add_period_constraint(self.crg.cd_clk200.clk, 5.0) + platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.crg.cd_clk200.clk) self.submodules.rtm_identifier = RTMIdentifier() csr_devices.append("rtm_identifier")