From 85102e191e582803e0f29aed60a4685694be1414 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 23 Jan 2018 11:00:55 +0000 Subject: [PATCH] sayma_rtm: derive clocks automatically * also don't add false paths unless necessary --- artiq/gateware/targets/sayma_rtm.py | 6 ------ 1 file changed, 6 deletions(-) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 3dbaf51c4..bbd8fb589 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -81,13 +81,7 @@ class SaymaRTM(Module): csr_devices = [] self.submodules.crg = CRG(platform) - self.crg.cd_sys.clk.attr.add("keep") clk_freq = 125e6 - platform.add_period_constraint(self.crg.cd_sys.clk, 8.0) - platform.add_period_constraint(self.crg.cd_clk200.clk, 5.0) - platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.crg.cd_clk200.clk) self.submodules.rtm_identifier = RTMIdentifier() csr_devices.append("rtm_identifier")