From 8119000982eab514ac7c189e071de6569bfd589e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 31 Jan 2019 19:43:54 +0800 Subject: [PATCH] sayma_rtm_drtio: use Si5324 soft reset Needs easy board rework to cut trace at pin 1 of Si5324. The Si5324 contains an internal pull-up on that pin. Allows using Si5324 + HMC7043 chips at the same time. Allows the Si5324 bypass hack for DDMTD experiments on the RTM. --- artiq/gateware/targets/sayma_rtm_drtio.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_rtm_drtio.py b/artiq/gateware/targets/sayma_rtm_drtio.py index 22226aa87..bdff03b2f 100755 --- a/artiq/gateware/targets/sayma_rtm_drtio.py +++ b/artiq/gateware/targets/sayma_rtm_drtio.py @@ -138,13 +138,12 @@ class _SatelliteBase(BaseSoC): platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser") - self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("hmc7043_reset")) - self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None + self.config["SI5324_SOFT_RESET"] = None rtio_clk_period = 1e9/rtio_clk_freq gtp = self.drtio_transceiver.gtps[0]