occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

rtio: do not reset DDS and SPI PHYs on RTIO reset (#503)

This commit is contained in:
Sebastien Bourdeauducq 2016-07-09 10:07:19 +08:00
parent e0ed99cd7b
commit 7a2405146a
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/rtio/phy/dds.py
View File

@ -6,7 +6,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
class _AD9xxx(Module):
def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
self.submodules._ll = ClockDomainsRenamer("rio")(
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
ad9xxx.AD9xxx(pads, **kwargs))
self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
self.rtlink = self._rt2wb.rtlink

2
artiq/gateware/rtio/phy/spi.py
View File

@ -6,7 +6,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
class SPIMaster(Module):
def __init__(self, pads, **kwargs):
self.submodules._ll = ClockDomainsRenamer("rio")(
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
SPIMasterWB(pads, **kwargs))
self.submodules._rt2wb = RT2WB(2, self._ll.bus)
self.rtlink = self._rt2wb.rtlink