From 78d1f0fdf6695c4760e0173fe692d82f89639b86 Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Tue, 4 Jul 2017 11:56:01 +0200
Subject: [PATCH] sawg: fix PhasedAccu resets

---
 artiq/gateware/dsp/accu.py | 10 ++++------
 artiq/gateware/dsp/sawg.py |  1 +
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/artiq/gateware/dsp/accu.py b/artiq/gateware/dsp/accu.py
index 9e583b110..79e297883 100644
--- a/artiq/gateware/dsp/accu.py
+++ b/artiq/gateware/dsp/accu.py
@@ -74,14 +74,12 @@ class PhasedAccu(Module):
 
         a = MCM(width, range(parallelism + 1))
         self.submodules += a
-        z = [Signal(width) for i in range(parallelism)]
+        z = [Signal(width, reset_less=True) for i in range(parallelism)]
         o = self.o.payload.flatten()
-        for oi in o:
-            oi.reset_less = True
-        load = Signal()
-        clr = Signal()
+        load = Signal(reset_less=True)
+        clr = Signal(reset_less=True)
         p = Signal.like(self.i.p)
-        f = Signal.like(self.i.f)
+        f = Signal.like(self.i.f, reset_less=True)
         fp = Signal.like(self.i.f)
         self.comb += [
             self.i.ack.eq(self.o.ack),
diff --git a/artiq/gateware/dsp/sawg.py b/artiq/gateware/dsp/sawg.py
index f13ecf79b..2ac997ad2 100644
--- a/artiq/gateware/dsp/sawg.py
+++ b/artiq/gateware/dsp/sawg.py
@@ -56,6 +56,7 @@ class SplineParallelDUC(Module):
         ]
 
         assert p.latency == 1
+        accu.i.clr.reset_less = True
         self.sync += [
             accu.i.clr.eq(0),
             If(p.i.stb,