forked from M-Labs/artiq
zotino: style, use attributes to set SPI config
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22557294ac
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@ -13,7 +13,6 @@ from artiq.language.core import (kernel, portable, delay_mu, delay, now_mu,
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from artiq.language.units import ns
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from artiq.language.units import ns
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice import spi2 as spi
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SPI_AD53XX_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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SPI_AD53XX_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |
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@ -8,7 +8,6 @@ from artiq.language.core import kernel
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice.ad53xx import SPI_AD53XX_CONFIG, AD53xx
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from artiq.coredevice.ad53xx import SPI_AD53XX_CONFIG, AD53xx
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_SPI_DAC_CONFIG = SPI_AD53XX_CONFIG
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_SPI_SR_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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_SPI_SR_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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@ -17,6 +16,7 @@ _SPI_SR_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
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_SPI_CS_DAC = 1
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_SPI_CS_DAC = 1
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_SPI_CS_SR = 2
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_SPI_CS_SR = 2
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class Zotino(AD53xx):
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class Zotino(AD53xx):
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""" Zotino 32-channel, 16-bit 1MSPS DAC.
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""" Zotino 32-channel, 16-bit 1MSPS DAC.
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@ -49,5 +49,5 @@ class Zotino(AD53xx):
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"""
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"""
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self.bus.set_config_mu(_SPI_SR_CONFIG, 8, self.div_write, _SPI_CS_SR)
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self.bus.set_config_mu(_SPI_SR_CONFIG, 8, self.div_write, _SPI_CS_SR)
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self.bus.write(leds << 24)
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self.bus.write(leds << 24)
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self.bus.set_config_mu(_SPI_DAC_CONFIG, 24, self.div_write,
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self.bus.set_config_mu(SPI_AD53XX_CONFIG, 24, self.div_write,
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_SPI_CS_DAC)
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self.chip_select)
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