forked from M-Labs/artiq
Bootloader: SDRAM patch for EFC
- Modification of the CFG flag ensure EFC to initialize DDRPHY correctly Note that Kasli and EFC share the same model of SDRAM
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c206e92f29
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@ -217,7 +217,7 @@ mod ddr {
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ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1));
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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#[cfg(any(soc_platform = "kasli", soc_platform = "efc"))]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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@ -308,7 +308,7 @@ mod ddr {
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let mut max_seen_valid = 0;
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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#[cfg(any(soc_platform = "kasli", soc_platform = "efc"))]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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@ -371,7 +371,7 @@ mod ddr {
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// Set delay to the middle
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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#[cfg(any(soc_platform = "kasli", soc_platform = "efc"))]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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