From 7429ee4fb63316b05da07407d6802670ebdb80fd Mon Sep 17 00:00:00 2001
From: Chris Ballance <chris.ballance@physics.ox.ac.uk>
Date: Thu, 11 Jan 2018 23:34:59 +0000
Subject: [PATCH] firmware: make read leveling robust for KUS SDRAM

Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
---
 artiq/firmware/libboard/sdram.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/firmware/libboard/sdram.rs b/artiq/firmware/libboard/sdram.rs
index f924f2df1..f2b320c93 100644
--- a/artiq/firmware/libboard/sdram.rs
+++ b/artiq/firmware/libboard/sdram.rs
@@ -207,7 +207,7 @@ mod ddr {
 
             // Get a bit further into the working zone
             #[cfg(kusddrphy)]
-            for _ in 0..8 {
+            for _ in 0..16 {
                 delay.set(delay.get() + 1);
                 ddrphy::rdly_dq_inc_write(1);
             }