From 735d28be71ac7839381c7b9fe816b2dcffcf0f19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Bourdeauducq?= Date: Mon, 19 Aug 2024 23:01:10 +0800 Subject: [PATCH] coredevice/ad9914: adapt to new binary shift typing --- artiq/coredevice/ad9914.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/artiq/coredevice/ad9914.py b/artiq/coredevice/ad9914.py index 12f6dbafd..bd2b5755c 100644 --- a/artiq/coredevice/ad9914.py +++ b/artiq/coredevice/ad9914.py @@ -243,9 +243,9 @@ class AD9914: # Enable autoclear phase accumulator and enables OSK. self.write(AD9914_REG_CFR1L, 0x2108) fud_time = now_mu() + int64(2) * self.write_duration_mu - pow -= int32((ref_time_mu - fud_time) * self.sysclk_per_mu * int64(ftw) >> int64(32 - 16)) + pow -= int32((ref_time_mu - fud_time) * self.sysclk_per_mu * int64(ftw) >> (32 - 16)) if phase_mode == PHASE_MODE_TRACKING: - pow += int32(ref_time_mu * self.sysclk_per_mu * int64(ftw) >> int64(32 - 16)) + pow += int32(ref_time_mu * self.sysclk_per_mu * int64(ftw) >> (32 - 16)) self.write(AD9914_REG_POW, pow) self.write(AD9914_REG_ASF, asf) @@ -319,9 +319,9 @@ class AD9914: self.write(AD9914_GPIO, (1 << self.channel) << 1) self.write(AD9914_REG_DRGAL, int32(xftw) & 0xffff) - self.write(AD9914_REG_DRGAH, int32(xftw >> int64(16)) & 0x7fff) - self.write(AD9914_REG_DRGFL, int32(xftw >> int64(31)) & 0xffff) - self.write(AD9914_REG_DRGFH, int32(xftw >> int64(47)) & 0xffff) + self.write(AD9914_REG_DRGAH, int32(xftw >> 16) & 0x7fff) + self.write(AD9914_REG_DRGFL, int32(xftw >> 31) & 0xffff) + self.write(AD9914_REG_DRGFH, int32(xftw >> 47) & 0xffff) self.write(AD9914_REG_ASF, amplitude) self.write(AD9914_FUD, 0) @@ -340,7 +340,7 @@ class AD9914: frequency (extended resolution mode). """ return round64(2.0*float(int64(2)**int64(62))*frequency/self.sysclk) & ( - (int64(1) << int64(63)) - int64(1)) + (int64(1) << 63) - int64(1)) @portable def xftw_to_frequency(self, xftw: int64) -> float: